PRODUCT NAME |
Asymmetrical Double Gate Ultra-Thin SOI MOSFETs
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ABSTRACT |
Fully-depletion operation is mandatory requirement for ultra-scaled devices (i.e. < 45 nm technology) which only can be achieved either multi-gate (i.e. FinFET) or thin body Silicon-on-Insulator (SOI). Thin body SOI offers another interesting feature compared to any other technologies i.e. back-gate biasing. In this invention, we utilize asymmetrical contact from the top,
which provide improved performance and better controlled of short-channel effects in thin body and thin buried oxide of SOI MOSFETs.
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FILING COUNTRY |
Malaysia
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REG. NUMBER |
PI 2015700349
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INTELLECTUAL STATUS |
Patent Filing
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FILE DATE |
5/2/2015
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IP TYPE |
Patent
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YEAR APPLY |
2014
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DEPARTMENT |
NANO
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STAF NO / MATRIC NO |
MOHD KHAIRUDDIN BIN MD ARSHAD, 750214-02-6509, 0100311
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OWNER NAME |
UNIMAP
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EQUITY PERCENTAGE |
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NOTEL HP |
195541402
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