| ABSTRACT |
The present invention provides a high-performance cell configuration characterized by the sequential stack: FTO/GO/(MA0.5Cs0.5)2SnI6/PEDOT:PSS/Pt. A primary objective of this invention is to provide an architecture where a Graphene Oxide (GO) layer reduces the surface roughness of the conductive substrate (from 12.5 nm to a functional level) to facilitate the growth of a compact VOP morphology. Another objective is to utilize a poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) hole transport layer in direct contact with the VOP absorber to ensure low-resistance hole extraction, coupled with a Platinum (Pt) counter electrode deposited via slot-coating to provide superior catalytic activity and electrical contact.
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