PRODUCT NAME Asymmetrical Double Gate Ultra-Thin SOI MOSFETs
ABSTRACT Fully-depletion operation is mandatory requirement for ultra-scaled devices (i.e. < 45 nm technology) which only can be achieved either multi-gate (i.e. FinFET) or thin body Silicon-on-Insulator (SOI). Thin body SOI offers another interesting feature compared to any other technologies i.e. back-gate biasing. In this invention, we utilize asymmetrical contact from the top, which provide improved performance and better controlled of short-channel effects in thin body and thin buried oxide of SOI MOSFETs.
FILING COUNTRY Malaysia
REG. NUMBER PI 2015700349
INTELLECTUAL STATUS Patent Filing
FILE DATE 5/2/2015
IP TYPE Patent
YEAR APPLY 2014
DEPARTMENT NANO