| ABSTRACT |
In this invention, we perform motion estimation calculation using reduced bit resolution. The objective of this method is to reduce the energy consumption during motion estimation calculation in video compression hardware. In this invention, instead of using full bit pixel resolution during full search motion estimation, this method performs motion estimation in two steps. The first step is to perform low resolution search. The result of the low resolution search is further refined using full bit resolution search but in a search area that is quarter from the low resolution search area. During low resolution search, instead of performing static pixel truncation, this method performs bit selection method. In this invention, we select two neighboring pixel bits that are most suitable to be used during low resolution motion estimation search. Once the two preferred neighboring bit has been identified, the low resolution search will be performed using these selected bits. The result of this motion estimation search will be used as the search center for the full resolution search during the second search. The two neighboring bits are being used for ease of hardware implementation. By using the prearrange pixel bits, we can use the same memory hardware (SRAM), while reducing the memory access bandwidth during low resolution search.
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